Publication
Using a hardware coprocessor for message scheduling in fieldbus-based distributed systems
| dc.contributor.author | Fonseca, José A. | |
| dc.contributor.author | Martins, Ernesto V. | |
| dc.contributor.author | Neves, Paulo Alexandre | |
| dc.date.accessioned | 2011-01-27T16:02:13Z | |
| dc.date.available | 2011-01-27T16:02:13Z | |
| dc.date.issued | 2001 | |
| dc.description | “Copyright © [2001] IEEE. Reprinted from 8th IEEE International Conference on Electronics, Circuits and Systems. ISBN:0-7803-7057-0. This material is posted here with permission of the IEEE. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.” | por |
| dc.description.abstract | Fieldbus based distributed embedded systems used in real-time applications tend to be inflexible in what concerns changing operational parameters on-line. Recent techniques such as the planning scheduler can avoid this problem but do not show adequate responsiveness f o r automatic negotiation of parameter values. In this paper the use of ASIC based coprocessors f o r message scheduling is proposed to solve the problem. Such coprocessors can be used in the arbiter nodes of systems based on widely used producer-consumer fieldbuses like WorldFIP and CAN. A prototype built with a Xilinx FPGA is presented. First performance results are shown and analyzed. They demonstrate that the device is able to achieve the expected performance and also point to the possibility of evolution to an almost dynamic scheduling approach. | por |
| dc.identifier.citation | FONSECA, J.A.; MARTINS, E.V.; NEVES, P. - Using a hardware coprocessor for message scheduling in fieldbus-based distributed systems. In IEEE International Conference on Electronics, Circuits and Systems, 8, Malta, 2 a 5 de Setembro de 2001. ICECS 2001. [S.l] : IEEE, 2001. ISBN 0-7803-7057-0. Vol.3, p.1485-1490 | por |
| dc.identifier.isbn | 0-7803-7057-0 | |
| dc.identifier.uri | http://hdl.handle.net/10400.11/527 | |
| dc.language.iso | eng | por |
| dc.peerreviewed | yes | por |
| dc.publisher | IEEE | por |
| dc.relation.publisherversion | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=957496&tag=1 | por |
| dc.subject | Hardware co-processor | por |
| dc.subject | FPGA - Fiel Programmable Gate Arrays | por |
| dc.subject | Controller area network | por |
| dc.subject | Message scheduling in fieldbus systems | por |
| dc.subject | Fieldbus | por |
| dc.title | Using a hardware coprocessor for message scheduling in fieldbus-based distributed systems | por |
| dc.type | conference object | |
| dspace.entity.type | Publication | |
| oaire.citation.conferencePlace | Malta | por |
| oaire.citation.endPage | 1490 | por |
| oaire.citation.startPage | 1485 | por |
| oaire.citation.title | 8th IEEE International Conference on Electronics, Circuits and Systems. ICECS 2001. | por |
| person.familyName | Neves | |
| person.givenName | Paulo Alexandre | |
| person.identifier.orcid | 0000-0002-7958-973X | |
| rcaap.rights | openAccess | por |
| rcaap.type | conferenceObject | por |
| relation.isAuthorOfPublication | c90b1bfb-be87-49f0-ae6e-f149a11f9009 | |
| relation.isAuthorOfPublication.latestForDiscovery | c90b1bfb-be87-49f0-ae6e-f149a11f9009 |
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